The present invention relates generally to the manufacture of semiconductor devices, and more particularly to manufacturing semiconductor devices that include lightly-doped diffusion (LDD) regions and self-aligned contact structures on the same substrate.
A continuing goal in the manufacture of semiconductor devices is increased density and miniaturization. Such goals can be particularly important in memory devices, such as dynamic random access memories (DRAMs), which may include millions of repeated memory cells. One way to increase device density can be to reduce the space between adjacent structures. For example, in semiconductor devices that include circuit devices, such as insulated gate field effect transistors (IGFETs), it can be desirable to reduce inter-gate spacing.
Reduced inter-gate spacing can present difficulties in forming contacts (including vias). Semiconductor devices can typically include one or more layers that may be connected to one another with contacts. To reduce spacing, and thereby increase density, it can be desirable to place such contacts as close as possible to adjacent structures, such as transistor gates. A preferred method of forming closely spaced contacts is to form self-aligned contacts. Self-aligned contact methods are disclosed in Japanese Patent Application Laid-Open No. Hei 9-134956 and Japanese Patent Application Laid-Open No. Hei 10-144633.
Referring now to FIG. 2A, a conventional approach to forming self-aligned contacts may include forming isolation regions 102 and a gate insulator 103 on a semiconductor substrate 101. Isolation regions 102 and/or a gate insulator 103 may comprise silicon dioxide. A transistor gate layer 104 may then be formed over the semiconductor substrate 101. A gate layer 104 may comprise polycrystalline and/or amorphous silicon (referred to herein collectively as polysilicon) doped with an impurity. A top insulating layer 105 may then be formed over a transistor gate layer 104.
A gate pattern (not shown) may then be formed over a top insulating layer 105 that contains a desired gate shape. A gate pattern may comprise a resist, such as photoresist, formed with a patterning process such as a lithography process or the like. Anisotropic etching can then transfer the gate pattern to form a top insulating layer 105, gate layer 104 and/or gate insulator 103 with a predetermined shape, as shown in FIG. 2A.
A sidewall insulating film can then be formed over patterned gate structures. A sidewall insulating film may comprise silicon dioxide deposited with chemical vapor deposition (CVD) techniques, for example. An etch back step may then remove the sidewall insulating film to form sidewalls 106. A top insulating layer 105 and sidewalls 106 can serve to protect a gate layer 104 from subsequent etching steps. In particular, such structures can prevent a gate layer 104 from being exposed when a contact hole is formed in close proximity to a gate layer 104.
A first and second etch stop layer, 108 and 107, may then be formed over a substrate. A first etch stop layer 108 may comprise silicon nitride. A second etch stop layer 107 may comprise silicon dioxide. An etch stop layer may prevent a semiconductor substrate 101 from being exposed when a contact hole is formed.
Following the formation of etch stop layers (108 and 107), an interlayer insulating film 109 may be formed. An interlayer insulating film 109 may comprise silicon dioxide. A contact hole etch mask 110 may then be formed over the interlayer insulating film 109. A contact hole etch mask 110 may include openings at the desired location of a contact hole. A conventional semiconductor device following the formation of a contact hole etch mask is shown in FIG. 2A. A contact hole etch mask 110 may comprise a layer of patterned resist, or the like.
Referring now to FIG. 2B, a conventional method may continue with a first contact hole etch. A first contact hole etch may be an anisotropic etch that is selective to a first etch stop layer 108. Thus, following a first contact hole etch, a contact hole may be formed through an interlayer insulating film 109 to expose etch stop layer 108. A conventional semiconductor device following a first contact hole etch is shown in FIG. 2B.
A second contact hole etch may then occur that is also anisotropic and selective to second etch stop layer 107. Such an etching can remove a first etch stop layer 108 at the bottom of a contact hole and expose a second etch stop layer 107. A third contact hole etching may then remove the second etch stop layer 107 at the bottom of a contact hole, thereby exposing a semiconductor substrate 101 at the bottom of a contact hole 113. A conventional semiconductor device following all contact hole etching steps is shown in FIG. 2C.
Referring once again to FIG. 2C, once a contact hole 113 is formed, the contact hole 113 may be filled with a conducting material. In this way a self-aligned contact may be formed. The contact may be self-aligned, as there is no minimum spacing requirement between a gate layer 104 and a contact due to the protection provided by a sidewall 106 and/or top insulating layer 105.
In addition to reductions in inter-gate spacing, miniaturization has also resulted in smaller gate lengths for IGFETs. Unfortunately, smaller gate lengths can lead to short channel effects and hot carrier effects, which can adversely affect transistor performance and/or reliability. One way to address such adverse effects can be to form transistors with lightly doped diffusion (LDD) regions (also referred to as lightly doped drains).
A conventional approach to forming LDD regions is disclosed in Japanese Patent Application Laid Open No. Hei 7-202179. The LDD structure is formed in the manufacture of a metal-oxide-semiconductor (MOS) type IGFET.
Referring now to FIG. 3A, a conventional method of forming MOS transistors with LDD regions can include forming isolation regions 202 and a gate insulator 203 on a semiconductor substrate 201. A transistor gate layer 204 may then be formed over the semiconductor substrate 201. A top insulating layer 205 may then be formed over a transistor gate layer 204. A gate etch mask (not shown) may then be formed over a top insulating layer 205. A gate etch mask may include a desired gate shape.
Anisotropic etching can transfer a gate pattern from a gate etch mask to the top insulating layer 205, gate layer 204 and/or gate insulator 203 to form a predetermined shape, as shown in FIG. 3A.
Isolation regions 202 and/or a gate insulator 203 may comprise silicon dioxide. A gate layer 204 may comprise polysilicon doped with an impurity. A top insulating layer 205 may comprise silicon dioxide. A gate etch mask may comprise a resist, such as photoresist, formed with a patterning process such as a lithography process, or the like.
Referring now to FIG. 3B, a LDD ion implantation step may then be performed. A LDD ion implantation may be a blanket implant at an injection dosage and energy that are relatively small with respect to a subsequent source/drain implant discussed below. In an LDD ion implantation step, a structure formed by top insulating layer 205, gate layer 204 and gate insulator 203 may serve as an implantation mask. LDD regions are shown as items 207 in FIG. 3B.
Following a LDD implant step, a sidewall insulating film can then be formed over a semiconductor substrate 201. A sidewall insulating film may then be etched back to form sidewalls 206. A sidewall insulating film may comprise CVD silicon dioxide. A conventional semiconductor device following the formation of sidewalls 206 is shown as item FIG. 3C.
Referring now to FIG. 3D, following the formation of sidewalls 206, a source/drain ion implantation step may be performed. A source/drain ion implantation may be a blanket implant at an injection dosage and energy that are relatively large with respect to the LDD implant step discussed above. In a source/drain ion implantation step, a structure formed by sidewalls 206, top insulating layer 205, gate layer 204 and gate insulator 203 may serve as an implantation mask. Source/drain regions are shown as items 208 in FIG. 3D. It is noted that an implantation mask for a source/drain implant can cover at least a portion of an LDD region. Consequently, as shown in FIG. 3D, LDD regions 207 can remain between source/drain regions 208 and a channel region formed below a transistor gate.
While self-aligned contacts and transistors with LDD regions can result in greater miniaturization and density in a semiconductor device, the inclusion of such features can raise problems in a manufacturing process.
One problem may occur in devices that have a high density region (such as a memory cell array) and another region with LDD regions (such as a periphery region). In particular, because a high density region may have very small inter-gate spacing, a sidewall etch back step may not sufficiently remove a sidewall insulating layer from between gates in a memory cell array. For example, a high density region on a semiconductor device may have inter-gate spacing of 0.2 microns (um) or less. At the same time, a sidewall for an LDD region may be about 0.1 um. Thus, when 0.1 um sidewalls are formed in an inter-gate spacing of 0.2 um or less, a sidewall etch back step may not be capable of clearing inter-gate spaces in the high density region. It is noted that such a problem may be increasingly difficult to address as miniaturization and density continue to increase.
Referring now to FIGS. 4A to 4D, a conventional manufacturing process for a semiconductor device having a high density region and LDD regions is shown in a series of cross sectional views. FIGS. 4A to 4D show a semiconductor device having a DRAM memory cell region Rmc, which can be a high density region, and a peripheral circuit region Rpc, which can be a LDD region.
Referring now to FIG. 4A, a method may include forming isolation regions 302 and a gate insulator (not shown) on a semiconductor substrate 301. A transistor gate layer 304 may then be formed over the semiconductor substrate 301. A top insulating layer 305 may then be formed over a transistor gate layer 304. A gate etch mask (not shown) may then be formed over a top insulating layer 305. Isolation regions 302 and/or a gate insulator may comprise silicon dioxide. A gate layer 304 may comprise polysilicon doped with an impurity. A top insulating layer 305 may comprise silicon dioxide.
A gate etch mask (not shown) may then be formed over a top insulating layer 305 that includes a desired gate pattern. Anisotropic etching can transfer a gate pattern from a gate etch mask to the top insulating layer 305, gate layer 304 and/or gate insulator, to form gate structures. Gate structures are shown in FIG. 4A.
Referring now to FIG. 4B, a LDD and array source/drain ion implants may then be performed. A LDD ion implantation may be an implant for peripheral regions having an injection dosage and energy that are relatively small with respect to a subsequent peripheral source/drain implant that follows. A LDD) ion implantation may form LDD regions 307 in peripheral circuit region Rpc. An array source/drain implant can form array source/drain regions 311 in memory cell region Rmc.
Referring now to FIG. 4C, a sidewall insulating film may then be formed over a semiconductor substrate 301. A sidewall insulating film may then be etched back to from sidewalls 306 in the peripheral circuit region Rpc and the memory cell region Rmc. A sidewall insulating film may comprise CVD silicon dioxide.
Referring now to FIG. 4D, following the formation of sidewalls 306, a peripheral source/drain ion implantation may be performed. A peripheral source/drain ion implantation step may be an implant on the peripheral circuit region Rpc at an injection dosage and energy that are relatively large with respect to the LDD implant step discussed above.
It is noted that FIG. 4D shows an case where inter-gate spacings in a memory cell region Rmc are sufficiently large enough to enable a sidewall etch back to expose a semiconductor substrate 301. An example of a case where inter-gate spacing in a memory cell region Rmc is smaller than that of FIG. 4D will now be described with reference to FIG. 5A.
As shown in FIG. 5A, in a memory cell region Rmc having smaller inter-gate spacing, inter-gate regions may not be sufficiently cleared of a sidewall insulating layer.
Referring now to FIG. 5B, a base insulating layer 312 may be formed over a semiconductor substrate 301. A base insulating layer 312 may provide insulation between various layers and may also serve as an etch stop.
An interlayer insulating film 309 can then be formed over base insulating layer 312. A contact hole etch mask (not shown) may then be formed over the interlayer insulating film 309. A contact hole etch mask may comprise resist and include openings at the desired location of a contact hole. Anisotropic etching may then form contact holes through interlayer insulating film 309 to base insulating layer 312, which may serve as an etch mask. In addition, additional etching within memory cell region Rmc can form a contact hole through base insulating layer 312, as shown in FIG. 5C.
Ideally, additional etching in memory cell region Rmc should expose a semiconductor substrate. However, as noted above, as inter-gate spacing decreases, sidewalls on opposing sides of a contact area can encroach on one another. Consequently, etching within a memory cell region Rmc may not clear a contact hole. Thus, as shown in FIG. 5D, in a peripheral circuit region Rpc, a contact hole 313 may extend to a base insulating layer 312. However, in a memory cell region Rmc, portions of a sidewall insulating film may undesirably remain at the bottom of contact holes 314.
Referring now to FIG. 5D, additional etching in a memory cell region may be performed to clear inter-gate spaces. However, such etching may undesirably expose a gate layer 304. Consequently, if a contact hole 314 is filled with a conducting material, a short circuit may be formed between such a conducting material and the exposed areas of a gate layer 304.
One approach to addressing the above-described drawback is shown in Japanese Patent Application Laid-Open No. Hei 8-139314. It is noted, however, that the method of Japanese Patent Application Laid-Open No. Hei 8-139314 forms a direct contact to a semiconductor substrate without forming an interlayer insulating film. Such a method will now be described with reference to FIGS. 6A to 6C.
A second conventional method may form structures such as those shown in FIG. 6A. Such structures may be formed with a similar method as described in conjunction with FIGS. 4A and 4B. Such structures may include a semiconductor substrate 301, isolation regions 302, a gate insulator (not shown), a transistor gate layer 304, a top insulating layer 305, LDD regions 307, and array source/drain regions 311. LDD regions 307 may be formed in a peripheral circuit region Rpc. Array source/drain regions 311 may be formed in a memory cell region Rmc.
Referring now to FIG. 6B, a base insulating layer 312 may then be formed over a semiconductor substrate 301. A base insulating layer 312 may comprise CVD silicon dioxide, for example. Unlike previously described conventional approaches, a polysilicon layer may then be formed over the surface of the device. Such a polysilicon layer may then be etched back, by an anisotropic etch for example, to form polysilicon sidewalls 306 in peripheral circuit region Rpc. Within memory cell region Rmc, inter-gate spaces may be filled with polysilicon.
Following the formation of polysilicon sidewalls 306, a peripheral source/drain ion implantation may be performed. A peripheral source/drain ion implantation step may be an implant in the peripheral circuit region Rpc at an injection dosage and energy that are relatively large with respect to a previous LDD implant step.
Referring now to FIG. 6C, an etch mask 310 may then be formed over a semiconductor substrate 301. An etch mask layer 310 may comprise a resist material, and include openings at the desired location of contact holes. Portions of a base insulating layer 312 at the bottom of such etch mask openings may then be removed to form contact holes 313 in the peripheral circuit region Rpc and the memory cell region Rmc. It is noted that within a memory cell region Rmc, such an etching step may include removing polysilicon exposed at the bottom of an etch mask opening. Such a step may include a etch having a high degree of selectivity between a polysilicon and the base insulating layer 312, which may comprise silicon dioxide.
As shown in FIG. 6C, because base insulating layer 312 is relatively thin with respect to top insulating layer 305, a semiconductor substrate can be exposed without exposing a gate layer 304. That is, a top insulating layer 305 may insulate the top of a gate layer 304 while remaining portions of a base insulating layer 312 may insulate the sides of a gate layer 304.
An etch mask 310 may then be removed, and a conductive wiring can be formed to active regions of a semiconductor substrate 301 through contact holes 313.
However, as noted above, the method of FIGS. 6A to 6C forms xe2x80x9cdirectxe2x80x9d contacts to a substrate and does not form an interlayer insulating film. If such a method was used in conjunction with an interlayer insulating film, it is believed that drawbacks could occur.
One drawback can be the overetching of the base insulating layer 312 and resulting exposure of a gate layer 304. With a gate layer 304 exposed, a short circuit may be result when a conductive material fills a contact hole. More particularly, an interlayer insulating film may comprise silicon dioxide, including undoped silicon dioxide (also referred to as nondoped silicate glass, or NSG) and borophosphosilicate glass (BPSG). At the same time, a base insulating layer 312 may also comprise silicon dioxide, as noted above. Consequently a contact hole etch could have no significant selectivity between a base insulating layer 312 and an interlayer insulating film, making it difficult to etch a contact hole without overetching the thin base insulating layer 312.
Another drawback can be the quality of a contact formed in a peripheral circuit region Rpc. As noted above, a contact hole etch could have no significant selectivity between a base insulating layer 312 and an interlayer insulating film. As a result, a base insulating layer 312 may not serve as an etch stop, and a contact hole can be overetched and/or underetched.
Another approach to forming contacts and LDD regions is shown in Japanese Patent Application Laid-Open No. Hei 10-200067, which shows a method of manufacturing a contact over bit line (COB) type DRAM. The method shows an approach in which sidewalls are formed to allow LDD regions to be created, and then removed to form contacts. However, the method does not show self-aligned contacts. The method will now be described with reference to FIGS. 7A to 8B.
Referring now to FIG. 7A, a p-type semiconductor substrate (PSUB) may include an n-well formed therein (NWELL). A p-well (PWELL) may be formed in the n-well. Isolation regions 420 and a gate insulating film (not shown) can be formed on the substrate. A gate layer may be formed that includes a layer of polysilicon 431a and tungsten silicide 431b. A gate etch mask (not shown) may be formed over a gate layer that includes a desired gate shape, and may be formed from a resist. An etching step may then be performed that forms gate electrodes 431. An ion implantation step may then form LDD regions 411.
Next, as shown in FIG. 7B, an etch stop film 421 of silicon dioxide may be formed over a substrate. A layer of polysilicon may then be formed over the etch stop film 421 and then etched back, with an anisotropic etch for example, to form polysilicon sidewalls 441. An ion implantation step may then form source/drain regions 412.
Next, as shown in FIG. 7C, polysilicon sidewalls 441 may be removed and a silicon nitride film 422 formed over etch stop film 421. A silicon nitride film 422 may be deposited with a reduced pressure CVD process to a thickness of several tens of nanometers. A process may also include forming a first interlayer insulating film 423 and a second interlayer insulating film 424. A first interlayer insulating film 423 may comprise NSG. A second interlayer insulating film 424 may comprise BPSG.
Next, as shown in FIG. 8D, a second interlayer insulating film 424 may be reflowed and leveled. A polysilicon film 442 may then be deposited, by a CVD method for example. An etch mask R1 may then be formed on polysilicon film 442. An etch mask R1 may be a patterned layer of resist, or the like.
Next, anisotropic etching can occur with etch mask R1 in place. Such anisotropic etching may stop above a gate electrode. A silicon nitride film 422 may protect a gate electrode 431 from being exposed by such an etch.
Referring now to FIG. 8E, another polysilicon film may then be deposited, by a CVD method or the like. Such a polysilicon film may then be etched, by anisotropic etching, to form polysilicon sidewalls 442a. Portions of a first insulating layer 423, silicon nitride film 422 and etch stop layer 421 may then be anisotropically etched to expose a substrate and form contact holes NCH and BCH.
Contact holes NCH and BCH may then be filled with polysilicon doped with an impurity to thereby form contacts.
In the previously described two methods, a base insulating film 312 and etch stop layer 421 may be formed from silicon dioxide. Thus, the material from which sidewalls are formed (sidewalls used to establish LDD regions) can be selected to have a high degree of etch selectivity with respect to silicon dioxide. Thus, such a sidewall material can be polysilicon.
In light of the above discussion, it would be desirable to arrive at some way of forming a semiconductor device that includes self-aligned contacts and LDD regions for devices having reduced spacings between structures, such as inter-gate spacings of 0.2 um and smaller.
According to the present invention, a method of manufacturing a semiconductor device can include implanting ions into an etch stop layer formed over a semiconductor substrate. An etch stop layer may then be heat treated to improve etch resistance which may have been affected by such an implanting of ions.
According to one aspect of the embodiments, a method may include forming a semiconductor device having a first area that includes lightly doped diffusion regions and a second area that includes self-aligned contacts formed with respect to reduced inter-gate spacing.
According to one aspect of the embodiments, a method may include forming a gate structure that includes a gate layer and top insulating layer, forming LDD regions in a first area and source/drain regions in a second area, and forming an etch stop layer over the first and second areas. A sidewall layer can then be formed over the etch stop layer, and then etched with a high selectivity with respect to the etch stop layer to form sidewalls in the first area while inter-gate spaces in a second area can remain filled with the sidewall layer. Source/drain regions may then be formed in the first area. A heat treatment can then take place. Sidewalls and portion of the sidewall layer in inter-gate spaces may then be removed. An interlayer insulating film can then be formed over the first and second areas. Contact holes may then be etched through the interlayer insulating film to expose portions of the semiconductor substrate. Contact holes may then be filled to form self-aligned contacts in at least the second area.